The present invention relates to a technology effective for application to a method of setting redundancy relieving information and trimming information such as a voltage employed in an electrically programmable erasable non-volatile memory, and to a technology effective for use in a flash memory, for example.
In a flash memory, nonvolatile storage or memory elements comprising MOSFETs formed in a two-layer structure having control and floating gates are used for memory cells. The amount of an electrical charge stored in the floating gate is changed to vary the threshold voltage of each MOSFET, thereby storing data in each memory cell.
This type of flash memory is generally provided with an internal power circuit having a booster circuit like a charge pump circuit for generating high voltages necessary for write/erase operations for each memory cell. However, the booster circuit causes predetermined variations even in the generated voltages due to variations in elements constituting the booster circuit. Even as to the MOSFETs constituting the storage elements of the flash memory, parameters such as the thickness or the like of a gate oxide film, the size of each portion of an element, the concentration of an impurity in a drain region, etc. vary due to the difference in process or the like, and correspondingly, a write characteristic and an erase characteristic vary in a predetermined range.
When the voltages generated by the booster circuit and the write and erase characteristics of each storage element vary as described above, the accurate operation of the memory is not assured. Therefore, there is known a technology wherein a trimming circuit is provided to make fine adjustments to each generated time and a write time at a stage subsequent to the fabrication of a chip. A general semiconductor memory including a flash memory is provided with a so-called redundant circuit for replacing a defective bit included in a memory array with its corresponding spare memory cell to improve the yield thereof.
It was conventionally common practice to adopt a system wherein the level setting of the trimming circuit and the setting of substitutional information by the redundant circuit were carried out by using a fuse (hereinafter called xe2x80x9cpolysilicon fusexe2x80x9d) formed of a polysilicon layer. However, the system using the polysilicon fuse needs a device for breaking or cutting off the polysilicon fuse by laser or the like. Since the subsequent change is unfeasible once it cuts off, the greatest possible care is required upon its cutting-off. A problem also arises in that trimming cannot be performed after the assembly of chips into packages. Therefore, there has also been proposed the invention related to a trimming circuit or a redundant circuit wherein elements identical in structure to nonvolatile storage or memory elements constituting a memory array, which are used in place of the polysilicon fuse, have been used in place of the polysilicon fuse.
However, the system using the nonvolatile memory elements in place of the polysilicon fuse is accompanied by the problem that since a memory element for a fuse is normally provided independently of a memory array, a dedicated circuit for effecting writing, verify, etc. on the memory element is needed to make circuit""s overhead greater, thereby increasing a chip size.
Therefore, the invention has also been proposed wherein a switching element is used in place of the polysilicon fuse, a trimming register for holding trimming information for controlling the switching element is provided and a relieving register for storing substitutional information therein is provided, and the trimming information and substitutional information are stored in a predetermined area lying within a memory array, whereby the information are read from the memory array upon resetting and set to the trimming register and relieving register (Unexamined Patent Publication No. Hei 11(1999)-297086).
However, the prior invention does not make it appear that in which area of the memory array the registers for the trimming information and relief should be stored. When one attempts to store the registers in a normal use area, a problem arises in that storage capacity available for a user is reduced. Further, there is a possibility that the user will accidentally rewrite data written into the trimming information storage areas A problem arises in that when the trimming information is rewritten or updated, the normal operation of a memory is not assured. Further, the registers for the trimming information and relief are provided in a controller, and the information is transferred to each register according to a normal read operation.
An object of the present invention is to make it possible to effect writing, verify, etc. on memory elements for storing trimming information and substitutional information or the like without the provision of a dedicated circuit in an electrically programmable erasable nonvolatile memory device like a flash memory.
Another object of the present invention is to make it possible to avoid a reduction in storage capacity available for a user and misrewriting of data by the user.
The above, other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
Substitutional information for a redundant circuit and adjustment information for a voltage trimming circuit are stored in some of a memory array, and these information are transferred to a latch circuit or a register upon power-up or the like.
Described more specifically, there is provided a nonvolatile semiconductor memory device comprising a memory array comprising a plurality of memory cells wherein which predetermined voltages are applied to selected memory cells to change threshold voltages thereof, thereby storing data therein according to the difference between the threshold voltages. In the nonvolatile semiconductor memory device, some in the memory array are used as spare memory cells, and at least one latch circuit connected to each bit line of the memory array through a transmission switch is provided. The memory array is capable of storing therein at least substitutional information for replacing a defective bit by the spare memory cell. The substitutional information is capable of being transferred from the memory array to the latch circuit through the transmission switch and held in the latch circuit.
According to the above means, since the substitutional information for the redundant circuit is originally stored in the part of the memory array, it is not necessary to use the polysilicon fuse. It is therefore possible to flexibly set substitutional information and trimming information for each memory cell and effect writing, verify, etc. on each memory or storage element for storing the substitutional information or the like therein without using a dedicated device or providing a dedicated circuit.
Preferably, the memory array includes a set value storage area whose access is restricted in a normal operating state and which is configured writably in a predetermined operation mode, and the substitutional information is capable of being stored in the set value storage area. Thus, the storage capacity available for each user is not reduced. It is also possible to avoid misrewriting of the substitutional information or the like by the user.
Further, the substitutional information stored in the memory array is transferred to and held in the latch circuit through the transmission switch upon power-up. It is thus possible to bring the substitutional information into a state of being held in the latch circuit when the normal operation is allowed.
The latch circuit has a positive-phase and a negative-phase input terminals. The pair of input terminals are connected to any two bit lines of the memory array, and the latch circuit captures memory information, based on complementary data stored in at least two memory cells connected to the two bit lines and holds the same therein. Thus, since the latch circuit is capable of capturing data to be held therein according to the differential, the reliability of the held data is enhanced.
The transmission switch may preferably be configured so that it is brought into conduction according to a reset signal supplied upon power-on to thereby allow the substitutional information stored in the memory array to be transferred to and held in the latch circuit. In the nonvolatile semiconductor memory device like the flash memory, there might be provided a terminal for inputting a reset signal from outside. Therefore, the substitutional information is transferred to and held in the latch circuit according to such an external reset signal, whereby it becomes unnecessary to provide any new circuit and terminal for the purpose of controlling the transmission switch.
A power-on reset circuit which detects the rising edge of a source voltage to generate a reset signal, is further provided. The transmission switch may be configured so as to be brought into conduction according to the reset signal generated by the power-on reset circuit. Thus, the substitutional information can be transferred to and held in the latch circuit before the supply of the reset signal from the outside. Further, even if the system is configured so as not to input the reset signal to the semiconductor memory device, the substitutional information can be transferred to and held in the latch circuit.
Furthermore, there are provided an internal power circuit which generates voltages used to write data into each memory cell in the memory array and erase the same therefrom, and a trimming circuit which adjusts the level of each of the voltages generated by the internal power circuit. Adjustment information for the trimming circuit and the substitutional information are stored in the memory array and transmitted to the latch circuit through the transmission switch. Thus, even when the adjustment information for the trimming circuit is set, the use of the polysilicon fuse is not necessary. Therefore, it is possible to improve the reliability and effect writing, verify, etc. on each memory element for storing the adjustment information or the like without using a dedicated device or providing a dedicated circuit.
A plurality of memory cells are respectively connected to respective bit lines in the set value storage area, the same data is stored in a plurality of memory cells connected to the same bit line, and the latch circuit determines and holds data, based on signals read from the plurality of memory cells having stored the same data therein. Thus, the set information held in the latch circuit is determined based on the information stored in the plural memory cells, and hence the reliability of the data held in the latch circuit is enhanced.
Further, the plurality of memory cells connected to the same bit line are respectively connected to discrete selection signal lines. A decoder is provided which selectively drives these selection signal lines. The selection signal lines are sequentially respectively driven to a selected level to thereby write data into memory cells in the set value storage area in turn. The information stored in the plurality of memory cells connected to the same bit line are simultaneously transferred to the latch circuit according to the simultaneous driving of the selection signal lines to the selected level. The nonvolatile semiconductor memory device generally needs much currents upon writing rather than upon reading. However, the writing is carried out in turn while the selection signal lines are sequentially selected, as described above, whereas the reading is collectively carried out. Thus, the current supply capacity of the internal power circuit need not increase as compared with the prior art, and the reading can be performed in a short time.
Furthermore, there is provided an external terminal to which a reset signal supplied from outside is inputted. The transmission switch is brought into conduction based on the reset signal generated by the power-on reset circuit or the reset signal inputted from the external terminal to thereby allow the data stored in the set value storage area to be transferred to and held in the latch circuit. Thus, since the data stored in the set value storage area can be transferred to and held in the latch circuit according to the reset signal supplied from outside and the internally-generated reset signal, the reliable transfer of data is enabled.
The latch circuit is provided with a switch element for allowing the setting of predetermined data for testing. When any information is not written into each memory cell, the state of the memory cell becomes instable and data to be transferred to the latch circuit is also unspecified. Therefore, while the test per se cannot be performed, predetermined information can be set to the latch circuit so as to allow entrance into a test operation. Based on the above result of test, the substitutional information and adjustment information may be written into the memory cells.
According to another invention of the present application, there are provided a memory array which comprises a plurality of memory cells in which predetermined voltages are applied to selected memory cells to change threshold voltages thereof, thereby storing data therein according to the difference between the threshold voltages, and which is provided with spare memory cells, and a latch circuit connected to bit lines of the memory array through a transmission switch. At least substitutional information for replacing a defective bit with the spare memory cell is stored in the memory array. In a nonvolatile semiconductor memory device wherein the substitutional information is transferred from the memory array to the latch circuit through the transmission switch and held in the latch circuit, writing and reading are effected on the memory array in a wafer state to detect a defective bit, and substitutional information for replacing the detected defective bit with the spare memory cell is written into a predetermined memory cell of the memory array. Thereafter, the wafer is cut every nonvolatile semiconductor memory device chips and they are encapsulated into packages respectively. Writing and reading are further effected on the memory array in the package state to detect a defective bit. Substitutional information for replacing the detected defective bit with the spare memory cell is written into a predetermined memory cell of the memory array, and the normally-written memory cell is extracted. Thus, the conventionally-unfeasible relief subsequent to package assembly is enabled and the yield of each product is improved.
Preferably, the substitutional information written into the memory cell can be read into the outside. Upon the writing of the substitutional information into the memory array in the package state, the substitutional information already written into the memory array is read and merged with substitutional information related to a newly-detected defective bit to obtain information, and the resultant information can be written into a predetermined memory cell of the memory array. Thus, it is not necessary to store the substitutional information written in the wafer state till after the assembly of each package. Further, there is no possibility that information about another product will accidentally be written due to mis-data management.
Further, in the nonvolatile semiconductor memory device including an internal power circuit which generates voltages used to write data into the memory array and erase the same therefrom, and a trimming circuit which adjusts the level of each of the voltages generated by the internal power circuit, each of the voltages generated by the internal power circuit is detected in both the wafer state and package state to determine adjustment information used for the trimming circuit. The adjusting information for the trimming circuit is written into the set value storage area together with the substitutional information. Thus, even when the adjustment information for the trimming circuit is set, the conventionally-unfeasible adjustment subsequent to the assembly of each package is allowed and hence the yield of each product is enhanced and the performance thereof such as a write time is improved.
A further invention of the present application provides a nonvolatile semiconductor memory device comprising a memory array which comprises a plurality of memory cells in which predetermined voltages are applied to selected memory cells to change threshold voltages thereof, thereby storing data therein according to the difference between the threshold voltages, and which is provided with spare memory cells, and a sense amplifier array which amplifies the potential of each bit line lying within the memory array. In the nonvolatile semiconductor memory device, a pad array used for input/output of write data and read data of the memory array is disposed along one side of a semiconductor chip with the memory array formed thereon. A latch circuit array is disposed between the data input/output pad array and the memory array. The latch circuit array is connected to the bit lines of the memory array through a transmission switch. Substitutional information stored in the memory array, for replacing the defective bit of the memory array with the spare memory cell is transferred to and held in the latch circuit array via the transmission switch. Further, a distribution circuit is disposed between the latch circuit array and the data input/output pad array and adapted to distribute write data to the sense amplifier array and distribute data read from each sense amplifier to each of pads. Thus, wiring routing can easily be performed between the memory array and the latch circuit array and between the latch circuit array and the distribution circuit.
Preferably, a set value storage area for storing the substitutional information is provided on the latch circuit array side of the memory array. Thus, the distance between the set value storage area for storing the substitutional information and the latch circuit array to which the substitutional information is transferred and which holds it therein, becomes short, and the information can accurately be transferred even upon power-up or the like.
Further, the memory array comprises a plurality of banks. Sense amplifier arrays are respectively disposed between any two banks, and the latch circuit array and distribution circuit are placed between the bank closest to the data input/output pad array, of the banks and the data input/output pad array. Thus, even when the sense amplifier arrays are provided in plural form, the latch circuit arrays and distribution circuits can easily be placed collectively at one point, and the size of the chip can be reduced.